1. A. Berman, Y. Birk, “Minimal Maximum-Level Programming: Faster Memory Access via Multi-Level Cell Sharing”, IEEE Global Communications Conference (GLOBECOM), 2013.
  2. A. Berman, Y. Birk, “Retired Page Utilization in Write-Once Memory – a Coding Perspective”, IEEE International Symposium on Information Theory (ISIT), 2013.
  3. O. Rottenstreich, A. Berman, Y. Cassuto, I. Keslassy, “Compression for Fixed-Width Memories”, IEEE International Symposium on Information Theory (ISIT), 2013.
  4. A. Berman, Y. Birk, “Utilizing Retired Pages for Improved Write Capacity of Solid-State Drives”, Annual Non-Volatile Memories Workshop (NVMW) 2013.
  5. A. Berman, Y. Birk, O. Rottenstreich, “Probabilistic Performance of Write-Once Memory with Linear WOM Codes – Analysis and Insights“, IEEE Allerton 2012.
  6. A. Berman, Y. Birk, “Memory Array Microarchitecture: Algorithmic Techniques for Density and Performance Enhancement“, Convention of IEEEI 2012.
  7. A. Berman, Y. Birk, “Low Complexity Two-Dimensional Data Encoding for Memory Inter-Cell Interference Reduction“, Convention of IEEEI 2012.
  8. A. Berman, Y. Birk, “Accelerating Flash Memory Access by Speculative Early Sensing Decision“, Annual Non-Volatile Memories Workshop (NVMW) 2012.
  9. A. Berman, Y. Birk, “Constrained Flash Memory Programming“, IEEE International Symposium on Information Theory (ISIT), 2011.
  10. A. Berman, Y. Birk, “Error Correction Scheme for Constrained Inter-Cell Interference in Flash Memory“, Annual Non-Volatile Memories Workshop (NVMW), 2011.
  11. A. Berman, Y. Birk, “Integrating De-Duplication and Write for Increased Endurance and Performance of Solid-State Drives“, Convention of IEEEI, 2010.
  12. A. Berman, R. Ginosar, I. Keidar, “Order is Power: Selective Packet Interleaving for Energy Efficient Networks-on-Chip“, IEEE/IFIP Int’l Conf. on VLSI and System-on-Chip (VLSI-SoC), 2010.
  13. A. Berman, I. Keidar, “Low Overhead Error Detection for Networks-on-Chip“, IEEE International Conference on Computer Design (ICCD), 2009.
  14. A. Berman, U.C. Weiser, “Reliable Architecture for Flash Memory“, Emerging Memory Technology Workshop, ACM/IEEE International Symposium on Computer Architecture (ISCA), 2009.
  15. R. Sahar, A. Lavan, A. Berman, E. Maayan, B. Eitan et-al., “A 4b/Cell 8Gb NROM Data-Storage Memory with Enhanced Write Performance“, IEEE Int’l Solid-State Circuits Conf. (ISSCC), 2008.